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Data Sheet
ADE7816
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T MIN to T MAX = ?40°C to +85°C. Note that, within
the timing tables and diagrams, the dual function pin names are referenced by the relevant function only; see the Pin Configuration and
Function Descriptions section for full pin mnemonics and function descriptions.
I 2 C-Compatible Interface Timing
Table 2. I 2 C-Compatible Interface Timing Parameters
Standard Mode
Fast Mode
Parameter
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for Repeated Start Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Suppressed Spikes
Symbol
f SCL
t HD;STA
t LOW
t HIGH
t SU;STA
t HD;DAT
t SU;DAT
t R
t F
t SU;STO
t BUF
t SP
Min Max
0 100
4.0
4.7
4.0
4.7
0 3.45
250
1000
300
4.0
4.7
N/A 1
Min Max
0 400
0.6
1.3
0.6
0.6
0 0.9
100
20 300
20 300
0.6
1.3
50
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
ns
1
N/A means not applicable.
SDA
t F
t SU;DAT
t HD;STA
t SP
t R
t BUF
SCL
t LOW
t R
t R
START
CONDITION
t HD;STA
t HD;DAT
t HIGH
t SU;STA
REPEATED START
CONDITION
t SU;STO
STOP
START
CONDITION CONDITION
Figure 2. I 2 C-Compatible Interface Timing
Rev. A | Page 5 of 48
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